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Вакансия находится в архиве
Требуемый опыт работы
От 3 до 6 лет
Тип занятости
Полная занятость
График работы
Полный день
IP Development department creates customizable microprocessor cores, technologies and software tools based on RISC-V ISA. Our clients and partners are key companies from US, Asia, Europe and Russia, developing computational platforms, storage systems, personal and smart devices, including high-performance heterogenous multicore systems with complex specialization and ISA extensions manufactured using the latest technologies up to 5nm.
We are active member of conferences and working groups on RISC-V standardization and open-source projects. Our open-source SCR1 core published under permissive license became one of the most popular RISC-V processor GitHub projects.
Purpose
Our team develops a generator of Verilog components used in the CPU cluster: coherent interconnect and AXI crossbar. The tool is used to increase productivity of hardware developers and verificators. The tool is used to generate components of various configurations including large CPU clusters that integrate dozens of CPU cores, System Level Cache banks and peripheral devices connected with thousands of individual wires.
Responsibilities
Practical skills
The following expertise would be an advantage:
We offer:
Ключевые навыки
Контактная информация
YADRO
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Вакансия опубликована 14.07.2024 в г. Санкт-Петербург.
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